The advent of wafer-level processing has allowed for substantial savings and efficiency in the creation of microprocessors, as has been widely recognized throughout the industry. Unfortunately, however, almost all wafers contain some bad die sites where defective dice are created. Time and materials are thus wasted on fabricating defective dice.
Attempts have been made to reduce the amount of expensive materials or processing time that is wasted on die sites that are known to be defective on a wafer. One such approach is to track the defective dice on each wafer. As the wafer is processed, initial probe testing of the die sites is conducted as is appropriate. Die sites that are known to be defective are tracked by the processing equipment and, where possible, are omitted from subsequent processing steps. As the dice are singulated, the defective sites, although singulated, are not separated or “picked” from the wafer. While this approach allows for some savings, it cannot eliminate the use of certain resources on the defective die sites, such as equipment for wafer-level testing and burn-in, which is not susceptible, due to its configuration, for contacting only known good dice, or KGD. It would also require processing equipment that is configured and designed to track each die site on each wafer and then apply treatments and testing only to selected sites, which, in most instances, is not feasible. Other approaches involve singulation of the wafer at an early stage, followed by testing and treatment of dice individually, or attempts to repair defects on dice. Such approaches can be costly in both the amount of handling, processing, and materials and in the additional processing time required.
A system or process that allows for the creation of a wafer that lacks any known defective die sites yet maintains the benefits of wafer-level processing would be advantageous. Such a process or method that could be used to form interconnect structures or add other functionality to a die would be further advantageous.